Escala™ Design Tools and Libraries

escala1 FFT’s at work

escala2VLIW CPU and IP libraries by Escala™

IC design flows typically employ industry standard tools such as Cadence, Mentor, and Synopsys. These are powerful tools and, they are the basis of every good design. We use these ourselves.

Sometimes industry standard is not enough. We began by building our own custom libraries. Then we extended to our own automatic code-generators, and finally we created a Very Large Instruction Word (VLIW) parallel processing multi-core synthesizers. After extensive validation and test trials, three years ago, we offered them to industry.

Escala™ design tools and libraries are used by some of the industry’s largest semiconductor manufacturers. Our IP libraries, featuring our highly configurable and efficient FFTs, are the signal processing engine for ICs that have shipped in the millions.

Escala™ VLIW CPU RTL code generator:

The EScala design platform greatly enhances productivity for complex algorithm definition, development, delivery, and support.

EScala is FAST

  • The user defines algorithms in C/C++ language.
  • EScala framework generates multiple instance of architecturally advantaged high performance cores along with performance/area/power metrics.
  • Fast and automated flow enables greater understanding of implementation options and tradeoffs.
  • Given the constraints and generated core instances, the user selects the best fit for the application at hand.
  • Fast models, design database, compilers, and tools generated on the fly.


  • Up to 32 operations per cycle
  • Up to 128 bytes per cycle memory access
  • Support for custom instructions (user provided and auto-generated)
  • Wide range of frequency support
  • Support for multiple cores

EScala is SMART

  • Increase design productivity through high-level language support of C/C++.
  • Optimizes power, performance, and area for architecturally tuned solution with a full top-down flow. The user provides code and sample use cases and EScala framework analyzes code traces to provide several flavors of cores with different area/performance tradeoffs for the user to select.
  • Preserves flexibility by providing C/C++ toolchain for the resulting tuned hardware platform so that algorithms can be tweaked after silicon has been frozen.

Please contact us for more information at:

EScala Product Briefpdf

EScala™ Signal Processing library:

Our ESP library consists of a IC-proven library of highly configurable signal processing blocks that we built over the last 10 years. Here are a few of the common blocks:

DSP Communications domain

  • FFT/1024/512 Low latency, dynamically configurable as 1024 or 512 points FFT and IFFT. Ideal for WiMax and MIMO applications. Detailed datasheet can be downloaded from pdfhere.
  • FFT 64/128: Low latency, 64 point FFT and IFFT. Parameterized bit widths and fixed point options. Supports flushing and re-starting the FFT operation instantly. Detailed datasheet can be downloaded from pdfhere.
  • Viterbi Decoder: Viterbi Algorithm for 802.11 a/b/g standard. Low gate count implementation. Option to optimize on flush latency with additional hardware. Detailed datasheet can be downloaded from pdfhere.

Security domain (Encryption and Authentication)

  • AES: High speed Advanced Encryption Standard. Supports AES FIPS 197 encryption and decryption. Detailed datasheet can be downloaded from here.
  • DES: Low-gate count Data Encryption Standard. Supports both encryption and decryption. Can be configured to implement Triple-DES. Detailed datasheet can be downloaded from pdfhere.
  • SHA-1 Hash: High speed data authentication. This IP core supports the Secure Hash Algorithm described in RFC 3174. Detailed datasheet can be downloaded from pdfhere.
  • MD5: High Speed data authentication. This IP core supports the MD5 Secure Hash Algorithm described in RFC 1321. Detailed datasheet can be downloaded from pdfhere.
  • ARC4: Multi-threaded stream ciphering algorithm. This IP core supports simultaneous encryption/decryption of multiple independent sessions in a time-multiplexed fashion. Detailed datasheet can be downloaded from pdfhere.

Error Control

  • ECC: High speed Error Correction Code encoder/decoder core, capable of Single bit Error Correction / Dual bit Error Detection (SECDEC) for DRAMs and high density SRAMs for an extensive range of data widths. Detailed datasheet can be downloaded pdfhere.

Esencia IP cores are among the best performance, low gate count IPs available in the market today. Each of these IP cores can be uniquely configured to meet any customer requirements.