Senior Design Engineer  (full-time; 1 position)

Senior Design Engineer  (full-time) 

Number of Positions: 1

Location:  Santa Clara, California.

Description:

Manage the design and verification process of modules used in integrated circuit systems for various clients. Oversee engineering sketches or specifications for installation of equipment, products, and systems. Perform simulation, synthesis, timing, and verification support.  Writing scripts, creating models, and interpreting service routine.

Requirements:

  • Must have a Master’s Degree (or foreign equiv) in Computer Science, Electrical Engineering, Electronics Engineering, Engineering (any), or related field, plus one year of Engineering experience using System Verilog Programming, SVN version control, and Modelsim.
  • We will also accept a Bachelor’s degree (or foreign equiv) in Computer Science, Electrical Engineering, Electronics Engineering, Engineering (any), or related field, plus five years of progressive post-bachelor’s experience in the Engineering field.
  • One year of the five years of progressive post-bachelor’s experience in the Engineering field must include experience using System Verilog Programming, SVN version control, and Modelsim.
  • All experience may be acquired concurrently. Any suitable combination of education, training, or experience is acceptable.

Send resumes to Esencia Technologies Inc, 2350 Mission College Blvd, Suite 490, Santa Clara, CA 95054; Ref: 02ET; EOE

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