Staff Verification Engineer (Job No. ESE16-7605)

Develop block-level and full-chip level verification environment for complex, mixed signal integrated circuits; define verification strategy; develop and implement test plans; create overall infrastructure verification methodology; design, develop, implement, and maintain test benches; write and execute test cases; identify bugs; develop solutions to correct problems; and provide guidance and support to Verification Engineer.  Requirements:  Master’s degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or related field of study and five years of verification experience or Bachelor’s degree and seven years of post-baccalaureate and progressive experience in verification.  Five years of work experience with ASIC verification using SystemVerilog, UVM/VMM/AVM, C, and Perl/Shell.

Please refer to Job Number ESE16-7605 when submitting resume.

Submit resume to:

Esencia Technologies, Inc.
3945 Freedom Circle, Suite 360
Santa Clara, CA 95054

ATTN:  Human Resources-Job No. ESE16-7605

E-mail:  hr@esenciatech.com

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