Staff Design Engineer (Job No. ESE16-2906)

Design FPGA (Field Programmable Gate Array) microprocessor/microcontroller, create prototype, design reusable register-transfer level (RTL) blocks for multiple architectures, develop requirements for firmware products, perform RTL code simulation, implement design in hardware, verify FPGA, diagnose and debug RTL related problems, conduct code review, and prepare and maintain design documentation.  Requirements – Master’s degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or related field of study and five years of hardware design experience or Bachelor’s degree and seven years of post-baccalaureate and progressive experience in hardware design.  Five years of work experience with Verilog RTL design and coding.

Please refer to Job Number ESE16-2906 when submitting resume.

Submit resume to:

Esencia Technologies, Inc.
3945 Freedom Circle, Suite 360
Santa Clara, CA 95054

ATTN:  Human Resources-Job No. ESE16-2906

E-mail:  hr@esenciatech.com

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