Staff Design Engineer (Job No. ESE16-1104)

Architect and develop SoC level complex ASIC verification environments; develop full-chip level test-benches and test cases to verify functionality of the digital integrated circuits; architect and develop efficient, reusable verification environment; create and implement detailed test plans; developed test cases, assertions, and functional coverage; implement cover points; execute testing; analyze code and functional coverage; identify and isolate design issues; and enhance current verification infrastructure.  Requirements:  Master’s degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or related field of study and five years of SoC verification experience or Bachelor’s degree and seven years of post-baccalaureate and progressive experience in SoC verification.  Five years of work experience with SoC verification, RTL design, RTL coding, code coverage, functional coverage, System Verilog/Verilog, OVM/UVM based verification methodology, C/C++, and Perl.

Please refer to Job Number ESE16-1104 when submitting resume.

Submit resume to:

Esencia Technologies, Inc.
3945 Freedom Circle, Suite 360
Santa Clara, CA 95054

ATTN:  Human Resources-Job No. ESE16-1104